Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include, for example, personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in one or more memory devices that are coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. For instance, random access memories such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) are used to temporarily store program information and data “actively” being used by the microprocessor. The data stored in random access memories may be read, erased, and rewritten many times during the execution of a program or function. Read only memories (ROMs) such as “write once read many” devices (WORMs) and electrically erasable programmable read only memories (EEPROMs), on the other hand, are used as long term memory devices which permanently store information about the microprocesor system or store software programs or instructions for performing specific functions until erased or deleted by a user, for example.
Random access memories tend to provide greater storage capability and programming options and cycles than read only memories, but they must be continually powered in order to retain their content. Most random access memories store data in the form of charged and discharged capacitors contained in an array of memory cells. Such memory cells, however, are volatile in that the stored charges will dissipate after a relatively short period of time because of the natural tendency of an electrical charge to distribute itself into a lower energy state. For this reason, most random access memories such as DRAMs must be refreshed, that is, the stored value must be rewritten to the cells, about every 100 milliseconds in order to retain the stored data in the memory cells. Even SRAMs, which do not require refreshing, will only retain stored data as long as power is supplied to the memory device. When the power supply to the memory device is turned off, the data is lost.
Read only memories presently used in microprocessor devices are non-volatile, that is, capable of retaining stored information even when power to the memory device is turned off. Some read only memory devices are constructed so that once programmed with data, they cannot be reprogrammed. Even those read only memories that can be reprogrammed have complex structures which are difficult to manufacture, occupy a large amount of space and consume large quantities of power. For these reasons, read only memories are unsuitable for use in portable devices and/or as substitutes for the frequently accessed random access memories, i.e., memories capable of 1014 programming cycles or more.
Efforts have been underway to create a commercially viable memory device that is both random access-type and nonvolatile. To this end, various implementations of such nonvolatile random access memory devices are presently being developed which store data in a plurality of memory cells by structurally or chemically changing the resistance across the memory cells in response to predetermined signals respectively applied to the memory cells. Examples of such variable resistance memory devices include memories using variable resistance polymers, perovskite, doped amorphous silicon or doped chalcogenide glass.
In a variable resistance memory cell, a first value may be written thereto by applying a signal having a predetermined voltage level to the memory cell, which changes the electrical resistance through the memory cell relative to the condition of the memory cell prior to the application of the signal. A second value, or the default value, may be written to or restored in the memory cell by applying a second signal to the memory cell, to thereby change the resistance through the memory cell back to the original level. The second signal has a voltage level in the negative direction from that of the first signal, and the voltage level of the second signal may or may not be the same magnitude as the voltage level of the first signal. Each resistance state is stable, so that the memory cells are capable of retaining their stored values without being frequently refreshed. In this regard, since the variable resistance materials can be “programmed” to any of the stable resistance values, such variable resistance memory cells are known as programmable conductor random access memory (PCRAM) cells.
The value of the PCRAM cell is read or “accessed” by applying a read signal to determine the resistance level across the cell. The voltage magnitude of the read signal is lower than the voltage magnitude of the signal required to change the resistance of the PCRAM cell. In a binary PCRAM cell, upon determining the resistance level of the PCRAM cell, the detected resistance level is compared with a reference resistance level. Generally, if the detected resistance level is greater than the reference level, the memory cell is determined to be in the “off” state, or storing a value of “0” On the other hand, if the detected resistance level is less than the reference level, the memory cell is determined to be in the “on” state, or storing a value of “1.”
FIG. 1 generally shows a basic composition of a PCRAM cell 10 constructed over a substrate 12, having a variable resistance material 16 formed between two electrodes 14, 18. One type of variable resistance material may be amorphous silicon doped with V, Co, Ni, Pd, Fe and Mn as disclosed in U.S. Pat. No. 5,541,869 to Rose et al. Another type of variable resistance material may include perovskite materials such as Pr1-xCaxMnO3(PCMO), La1-xCaxMnO3 (LCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO) as disclosed in U.S. Pat. No. 6,473,332 to Ignatiev et al. Still another type of variable resistance material may be a doped chalcogenide glass of the formula AxBy, where “B” is selected from among S, Se and Te and mixtures thereof, and where “A” includes at least one element from Group IIIA (B, Al, Ga, In, Tl), Group IVA (C, Si, Ge, Sn, Pb), Group VA (N, P, As, Sb, Bi), or Group VIIA (F, Cl, Br, I, At) of the periodic table, and with the dopant being selected from among the noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni, as disclosed in U.S. Published Application Nos. 2003/0045054 and 2003/0047765 to Campbell et al. and Campbell, respectively. Yet another type of variable resistance material includes a carbon-polymer film comprising carbon black particulates or graphite, for example, mixed into a plastic polymer, such as that disclosed in U.S. Pat. No. 6,072,716 to Jacobson et al. The material used to form the electrodes 14, 18 can be selected from a variety of conductive materials, such as tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among others.
In a bistable PCRAM cell, the programmable conductor memory element 104 stores a binary 0 when in a high resistance state, and a binary 1 when in the low resistance state. The memory element 104 is ideally programmed to the low resistance state, i.e., to store a binary 1, by applying a signal having a positive voltage with a magnitude at least that of the voltage of a threshold write signal, and can be restored to the high resistance state, i.e., to store a binary 0, by applying a signal having a negative voltage with a magnitude of at least that of the voltage of a threshold erase signal. Of course, the values “0” and “1” relative to the high and low resistance state, respectively, are user-defined, and thus could be reversed, with the high resistance state representing the value “1” and the low resistance state representing the value “0.” The memory element can be nondestructively read by applying to the memory element a reading signal having a voltage magnitude of less than the threshold write signal.
As with volatile RAMs, PCRAMs are arranged as an array of memory cells and are written, erased, and read using a controller. Examples of an electrical arrangement of individual PCRAM cells and also of an array of PCRAM cells is disclosed in copending and co-owned U.S. patent application Ser. No. 10/035,197, the contents of which are hereby incorporated by reference.
While the overall arrangement and operation of the different types of variable resistance PCRAMs may be similar regardless of the type of variable resistance material used in the memory elements, much research of late has focused on memory devices using memory elements having doped chalcogenide materials as the variable resistance material. More specifically, memory cells having a variable resistance material formed of germanium-selenide glass having a stoichiometry of GexSe100−x, with x ranging from about 20 to about 43, have been shown to be particularly promising for providing a viable commercial alternative to traditional DRAMs.
A specific example of such a chalcogenide PCRAM cell is shown in FIG. 2, in which a layer of an insulating material 24 such as silicon dioxide or silicon nitride formed over a substrate 22, a lower electrode 26 is formed over the insulating layer 24, a first layer of a chalcogenide material 28 formed over the electrode 26, a metal-containing layer 30 deposited over the first layer of chalcogenide material 28, a second layer of chalcogenide material 32 provided over the metal containing layer 30, and an upper electrode 34 formed overlying the second layer of chalcogenide material 32.
The material used to form the electrodes 26, 34 can be selected from a variety of conductive materials, for example, tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among many others. The insulating layer 24 may be formed of silicon nitride or any other conventional insulating nitride or oxide, among others. For the chalcogenide material layers 28, 32 a germanium-selenide glass having a stoichiometry of about Ge40Se60 has proven to be one of the more promising compositions among the chalcogenide glass compositions in PCRAMs. Each of the first and second chalcogenide material layers 28, 32 is formed to a thickness of approximately 150 Å.
The metal-containing layer 30 may be formed to a thickness of approximately 470 Å from any of a variety of silver-chalcogenide materials including silver selenide (e.g., Ag2Se), silver sulfide, silver oxide, and silver telluride, with silver selenide being preferred. Providing the metal-containing layer 30 over the first layer of chalcogenide material 28 and then providing a second layer of chalcogenide material 32 over the metal-containing layer 30 allows the metal in the metal-containing layer 30 to be more readily available to the chalcogenide material for switching the chalcogenide material between resistive states.
An exemplary process of manufacturing the variable resistance memory cell shown in FIG. 2 is disclosed in co-pending U.S. patent application Ser. No. 10/225,190, which is commonly assigned to the assignee of the present application, and the contents of which are hereby incorporated by reference.
Generally, a chalcogenide PCRAM cell, such as that having a structure described above with reference to FIG. 2, has an initial and “off” state resistance of over 100 K Ω (e.g., 1 M Ω). To perform a write operation on a chalcogenide memory cell in its normal high resistive state, a signal having at least a threshold voltage is applied to the electrode serving as the anode, with the cathode held at the reference potential or ground. Upon applying the threshold level voltage, i.e., a write signal, the resistance across the memory cell changes to a level dramatically reduced from the resistance in its normal state, to a resistance less than 100 K Ω (e.g., 20K Ω), whereupon the cell is considered to be in the “on” state.
The chalcogenide PCRAM cell retains this new lower level of resistivity until the resistivity is changed again by another qualifying signal applied to one of the electrodes of the cell. For example, the memory cell is returned to the high resistance state by applying an erase signal thereto having a voltage in the negative direction of the voltage applied in the write operation to achieve the lower resistance state. The voltage of the erase signal may or may not be the same magnitude as the voltage of the write signal, but is at least of the same order of magnitude.
Although it is not clearly understood what change or changes are induced in the memory cell by the application of the threshold potential to result in the stable low resistant state, it is believed that the metal ions incorporated into the chalcogenide material layer somehow become aligned into a low resistance conductive configuration between the electrodes once the voltage of the applied signal reaches the threshold level. At least two theories exist as to the precise nature of the alignment.
In one theory, the metal ions within the chalcogenide material begin to progress through the chalcogenide material toward the anode upon the application of a signal having the threshold voltage level of a write operation. The metal ions continue to agglomerate until a conductive dendrite or filament is extended between the electrodes to thereby interconnect the top and bottom electrodes to create an electrical short circuit. Upon application of a signal having the negative threshold voltage level, the dendrite recedes from the anode as the metal ions return to solution in the chalcogenide material or return to the source layer.
In a second theory, when an initial write signal having a threshold positive voltage level is applied to the memory cell, channels of the metal-containing layer, e.g., Ag2Se, are formed in the chalcogenide material, and the metal ions are caused to cluster along the channels. Upon application of an erase signal having a threshold negative voltage level to the cell, the metal ions are caused to move away from the channels, while the channels remain. Subsequent write signals cause the metal ions to re-cluster along the channels. The resistance through the cell in the write and erase states is thus determined by the amount of metal ions clustered along the channels.
The write and erase signals are applied via the circuitry of the overall memory device incorporating a memory of the chalcogenide PCRAM cells. A simplified illustration of a PCRAM programming circuit 50 is shown in FIG. 3A, in which a write signal having a voltage VTW is applied to the top electrode 34 of the PCRAM cell 20. In this example, VTW has a voltage level of +1.0 V and a pulse width, i.e., duration, of about 8 ns. As mentioned above, the natural state of a PCRAM cell is the high resistant state, which, for purposes of illustration, is designated here to correspond to the “off” state, or a binary value of “0.” Upon the application of VTW to top electrode 34 of PCRAM cell 20, the PCRAM cell 20 changes to a low resistance i.e., “on” state and, correspondingly, is written to store a binary value of “1.”
The relationship between voltage of a signal applied to the PCRAM cell and resistance in the cell for a write operation performed on a properly functioning cell is illustrated in FIG. 4A. The initial or normal resistance level of a PCRAM cell is shown as ROFF, which is above a minimum threshold level REMin in which the PCRAM cell is stable in a high resistance state. When the PCRAM cell is in the high resistance state and a signal of voltage VTW is applied to the cell, the resistance drops to the level indicated by RON, which is below a maximum threshold level RwMax in which the PCRAM cell is stable in a low resistance state.
FIG. 3B shows the same programming circuit 30 illustrated in FIG. 3A, except that an erase signal having a voltage VTE is applied to the bottom electrode 26. VTE has a voltage level of −0.75V and a pulse width of about 8 ns. Upon the application of a signal of voltage VTE to bottom electrode 26 of PCRAM cell 20, the PCRAM cell 20 returns to its high resistance state, i.e., its “off” state, by erasing the binary value of “1” previously written in the cell, so that the value of “0” is again stored in the PCRAM cell 20.
FIG. 4B shows the relationship between resistance through the PCRAM cell 20 and the voltage of a signal applied to the cell during an erase operation. As in FIG. 4A, RON indicates the resistance level of the PCRAM cell 20 in the low resistance (on) state, and RWMax, represents the maximum resistance value at which the PCRAM cell 20 is stable in the low resistance state, while ROFF indicates a resistance level of the PCRAM cell 20 in the high resistance (off) state, and REMin demonstrates the minimum resistance value at which the PCRAM cell 20 is stable in the high resistance state. When the PCRAM cell 20 is in the low resistance state and VTE is subsequently applied to the cell, the resistance in the PCRAM cell 20 increases to the level indicated by ROFF.
It is noted that the voltage VTW of the write signal is not necessarily of the same magnitude as the voltage VTE of the erase signal because a write signal seeks to overcome forces attributable to the physical separation of metal ions from the metal-containing layer 24 and to the diffusion into the variable resistance material 22 against the concentration gradient of the metal ion therein, inter alia, while an erase signal must overcome forces attributable to the agglomeration tendency of the metal ions in the variable resistance material 22 and to the “pushing” of the metal ions back into the metal-containing layer 24, inter alia. The voltage levels required to overcome each set of forces are thus not necessarily the same in the forward and backward directions.
It has been observed that after a number of write/erase operations, the resistance profiles of PCRAM cells such as those shown in FIG. 2, particularly PCRAM cells including a silver selenide layer, have a tendency to shift. Specifically, the cell may eventually write to an “on” state in which the resistance in that state is at an unacceptably high level, or an erase operation may place the cell in an “off” state in which the resistance in that state is at an unacceptably low level. In other cases, the resistance profile of the memory cell may shift so that the resistance in the “on” state is too low, or the resistance in the “off” state is too high. This can happen in as few as about 400 write and erase cycles, which is problematic in that typical life expectancies for random access memory devices are on the order of 1014 write/erase cycles. Thus, if the resistance drift is not corrected, the PCRAM memory devices will ultimately fail. The phenomenon of resistance drift will be described in further detail below, with reference to FIGS. 5A through 5D.
In the first case, the resistance profile of the chalcogenide material changes over time so that the resistance of the “on” state drifts unacceptably high. In this condition, the resistance in the PCRAM cell for the “on” state gradually becomes higher than the resistance RON shown in FIG. 4A. As the “on” state resistance drifts higher, application of signals at the threshold write voltage level become less and less effective to fully drive the resistance in the PCRAM cell to or below the maximum stable low resistance level RWMax of the low resistance “on” state. If left unchecked, the memory cell develops an underwrite condition in which application of a write signal will only be able to achieve a resistance RDW1 above the maximum stable low resistance RWMax, as seen in FIG. 5A. When this happens, the write signal voltage VTW is insufficient to switch the PCRAM cell to the stable “on” state, whereby the function of the PCRAM cell then fails.
In the second case, the resistance of the PCRAM cell drifts unacceptably low in the “off” state. When this happens after repeated write/erase cycles, the “off” state resistance achieved upon application of the erase signals at the threshold voltage VTE falls below the level ROFF shown in FIG. 4B. The resistance RDE1 achieved by an erase operation drifts increasingly lower until application of the threshold erase signal voltage VTE becomes insufficient to bring the memory cell to the minimum stable high resistance level REMin, as illustrated in FIG. 5B. Once this undererase condition is reached, subsequent erase operations will fail to erase the stored value in the PCRAM cell, causing a breakdown in the function of the PCRAM device.
In the third case, the resistance profile of the PCRAM cell changes so that the resistance level in the “on” state falls too far below the target level RON shown in FIG. 4B. While the “on” state is stable at the overwritten resistance level RDW2, application of a threshold erase signal to the cell is insufficient to drive the resistance level ROFF2 above the stable “off” resistance level REMin, as shown in FIG. 5C. Similarly to the situations described above, this overwrite condition causes the PCRAM cell to fail.
A fourth case can also occur in which the resistance profile of the PCRAM cell drifts to an overerase condition, in which the resistance level RDE2 in the “off” state becomes excessively high so that application of a threshold write signal is insufficient to drive the cell to an “on” state. Instead, application of the threshold write signal merely drives the PCRAM cell to a resistance level RON2, which is above the stable resistance level RWMax for the low resistance state, as shown in FIG. 5D. Again, this causes the PCRAM cell to fail.
Since the threshold voltages VTW and VTE for the write and erase signals often differ in magnitude relative to the zero voltage level, the direction of the resistance drift most likely occurs towards the direction having the higher threshold voltage magnitude. For example, in the embodiment described above with reference to FIGS. 4A and 4B, the PCRAM cell 20 may tend to drift towards either an undererase condition (a low resistance “off” state) or an overwrite condition (an excessively low resistance “on” state) because the magnitude of the threshold write signal voltage VTW is greater than the magnitude of the threshold erase signal voltage VTE. Similarly, when the threshold erase signal voltage is greater than the threshold write signal voltage, the PCRAM cell 20 may tend to drift towards either towards an overerase condition (an excessively high resistance “off” state) or an underwrite condition (a high resistance “on” state).
Also, in PCRAM memory devices, the necessary voltage level required to switch a memory cell from an “off” (erase) state to an “on” (write) state tends to decrease as the temperature of the cell rises. Thus, undererase and overwrite conditions, i.e., drift towards a low resistance “off” state and excessively low resistance “on” state, respectively, is more likely to occur at higher ambient and/or system temperatures.
Since the voltage levels of the write and erase signals are preset in the memory device so as to be consistently delivered to appropriate memory cells at the predetermined levels during performance of the write and erase functions, the predetermined voltage levels of the applied write and/or erase signals will at some point become insufficient to overcome the drifted threshold level(s) to perform the desired operation. Specifically, the relative concentration of metal ions in the chalcogenide material in the “on” state may build up to a point where subsequent applications of signals at the threshold voltage level used for erase operations may not be sufficient to switch the memory cell back to the high resistance “off” state. In an alternative scenario, the concentration of metal ions in the chalcogenide material may become so depleted or the conduction channels may be driven back into the source layer so that, subsequent applications of signals at the threshold voltage level used for write operations may be insufficient to switch the memory cell to the “on” state. Thus, the eventual effect of such resistance drift over time may cause the memory devices to fail.